Notes on the Text

Part I

1. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other connections.

粗略地说，晶体管好似一种电子控制阀，由此加在阀一端的能量（电压）可以使能量（电流）在另外两个端之间流动。

2. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and nonmetals.

查阅大学化学书中的元素周期表，你会查到半导体是介于金属与非金属之间的一类元素。

3. Phosphorous and boron are two elements that are used to dope N-type and P-type silicon, respectively.

N型硅半导体掺入磷元素，而P型硅半导体掺入硼元素。

4. The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the outside world.

半导体材料上制作晶体管或二极管所形成的小芯片用塑料封装以防损伤和被外界污染。

Part Ⅱ

1. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5000 gates to over 100 million.

随着特征尺寸的逐年缩小和设计工具的改进，ASIC中的最大复杂度从5000个门电路增长到了1亿个门电路，因而功能也有了极大的提高。

2. The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars.

不能循环的工程费用（建立工厂生产特定ASIC的成本）可能会达到数十万美元。

3. The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs.

专用集成电路这一通用名词也包括FPGA，但是大多数设计者仅将ASIC用于非现场可编程的器件，将ASIC和FPGA两者区别开来。

4. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.

尽管有第三方设计工具，但第三方设计工具和不同的ASIC制造商的布线以及实际半导体工艺过程的性能之间却缺乏有效的联系。

5. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in third party tools.

每个ASIC制造商都可以创造他们自己的具有已知电性能的功能块，如传播延迟器、电容、电感，这些都可以用第三方工具来表示（实现）。

6. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.

标准单元设计使门阵列和全定制设计之间在一次性投入的工程费用和循环元件成本方面相互适应。

·Non-recurring engineering (NRE) refers to the one-time cost of researching, designing, and testing a new product.

7. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.

以工业界普通的熟练水平实现的这些步骤几乎总是产生能正确实现原设计的最终器件，除非后来在物理制造过程中引入了缺陷。

8. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input nand, inverters, etc.

这些构成的元素是从一个标准单元库中得到的，这个库由事先规定好的门电路集合构成，例如2输入或非门、2输入与非门、非门等。

9. The significant difference is that Standard Cell design uses the manufacturer's cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design.

重要的差别在于标准单元设计使用制造商的单元库，这些库已用于数以百计的设计实现，因而比起全定制设计来风险小得多。

10. Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.

门阵列设计是一种制造方法，事先定义好扩散层（晶体管和其他有源器件），包含这些器件的晶片在金属化之前被库存，也就是说先不进行连接。

11. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization.

门阵列ASIC是一种折中方案，因为将某一给定的设计与制造商库存的晶片相对应总是不可能达到100%利用率的。

·as mapping … never gives … 表示原因。

12. Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.

现在电路设计者已经很少采用纯粹的逻辑门阵列设计，而几乎都代之以FPGA之类的现场可编程器件了。这些器件可由用户编程，使工具作业费用最低，以略为提高的零件价格获得可比的性能。

13. Today gate arrays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.

现在门阵列正在发展为结构化ASIC，其中包含很大的IP内核，如处理器、DSP单元、外围设备、标准接口、集成SRAM存储器以及一组可重新设置的未确定功能的逻辑单元。

·IP core (intellectual property core)：预先设计好、可复用、有知识产权的硬件或软件块。

14. The disadvantages can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.

缺点包括增加的制造和设计时间，增加的不可循环工程成本，更复杂的CAD系统，以及对设计团队熟练程度高得多的要求。

15. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers and pre-characterization of what is on the silicon.

不过结构化ASIC的基本前提是，由于有事先定义的金属层和事先规定了硅片上包含的内容，制造周期和设计周期相对于基于单元的ASIC都有所减少。