Technical Tips

RS flip-flop

The most fundamental latch is the simple RS flip-flop, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (negative OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low. If S is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R is pulsed high while S is held low,then the Q output is forced low, and stays low even after R returns low.

JK flip-flop

The JK flip-flop augments the behavior of the RS flip-flop by interpreting the S=R=1 condition as a “flip” or toggle command. Specifically, the combination J=1, K=0 is a command to set the flip-flop; the combination J=0, K=1 is a command to reset the flip-flop; and the combination J=K=1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J=K=0 does NOT result in a D flip-flop,but rather,will hold the current state.To synthesize a D flip-flop,simply set K equal to the complement of J.

D flip-flop

The Q output always takes on the state of the D input at the moment of a rising clock edge, and never at any other time. It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line.