第3章 QMEM剖析

`define OR1200_QMEM_IMPLEMENTED
`define OR1200_QMEM_IADDR    32'h0080_0000
`define OR1200_QMEM_IMASK    32'hfff0_0000    // QMEM中指令存储地址是
                                              //0x00800000-0x008fffff，所以共1MB
`define OR1200_QMEM_DADDR    32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 QMEM中数据存储地址与指令存储
                                              //地址可以不一样，默认是一样的
`define OR1200_QMEM_BSEL                    //默认是没有定义，但通过加载存储
                                            //类指令的分析可知必须有该定义
// QMEM interface acknowledge
// To enable qmem_ack port, define this macro.
//`define OR1200_QMEM_ACK            不需要这个定义

or1200_qmem_top.v
`ifdef OR1200_QMEM_IADDR
    assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) ==
`OR1200_QMEM_IADDR;
`else
    assign iaddr_qmem_hit = 1'b0;
`endif
`ifdef OR1200_QMEM_DADDR
    assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) ==
`OR1200_QMEM_DADDR;
`else
    assign daddr_qmem_hit = 1'b0;
`endif

iaddr_qmem_hit = (qmemimmu_adr_i & 32'hfff0_0000) == 32'h0080_0000;

`ifdef OR1200_QMEM_IADDR
assign iaddr_qmem_hit = 1'b1;
`else
    assign iaddr_qmem_hit = 1'b0;
`endif
`ifdef OR1200_QMEM_DADDR
assign daddr_qmem_hit = 1'b1;
`else
    assign daddr_qmem_hit = 1'b0;
`endif

or1200_defines.v
`ifdef OR1200_NO_IMMU            //在我们的最小系统中没有配置IMMU
        ……
    assign qmemimmu_adr_o = icpu_adr_i;
    assign icpu_tag_o = qmemimmu_tag_i;
    assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
                                  //page_cross表示前后两次指令的地址是否位于不同
                                  //的内存页，OR1200中默认内存页是8KB，当位于不
                                  //同的页时page_cross为1，反之为0，笔者认为当
                                  //没有配置使用IMMU时，page_cross其实没有作用，
                                  //可以去掉，所以此处可以直接改为
                                  //assign qmemimmu_cycstb_o = icpu_cycstb_i
    assign icpu_rty_o = qmemimmu_rty_i;
    assign icpu_err_o = qmemimmu_err_i;
    ……
`else
    ……

or1200_qmem_top.v
//QMEM与CPU、IMMU之间信号
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
// QMEM与ICache之间
assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;

//QMEM与CPU、IMMU之间信号
assign qmemicpu_dat_o = icqmem_dat_i;
assign qmemicpu_ack_o = icqmem_ack_i;
assign qmemimmu_rty_o = icqmem_rty_i;
assign qmemimmu_err_o = icqmem_err_i;
assign qmemimmu_tag_o = icqmem_tag_i;
// QMEM与ICache之间
assign icqmem_adr_o = qmemimmu_adr_i;
assign icqmem_cycstb_o = qmemimmu_cycstb_i;
assign icqmem_ci_o = qmemimmu_ci_i;
assign icqmem_sel_o = qmemicpu_sel_i;
assign icqmem_tag_o = qmemicpu_tag_i;

or1200_dmmu_top.v
`ifdef OR1200_NO_DMMU                      //在我们的最小系统中没有配置DMMU
    assign qmemdmmu_adr_o = dcpu_adr_i;
    assign dcpu_tag_o = qmemdmmu_tag_i;
    assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
    assign dcpu_err_o = qmemdmmu_err_i;
`else
    ……

or1200_qmem_top.v
//QMEM与CPU、DMMU之间的信号
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
//QMEM与DCache之间的信号
assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;

//QMEM与CPU、DMMU之间的信号
assign qmemdcpu_dat_o = dcqmem_dat_i;
assign qmemdcpu_ack_o = dcqmem_ack_i;
assign qmemdcpu_rty_o = dcqmem_rty_i;
assign qmemdmmu_err_o = dcqmem_err_i;
assign qmemdmmu_tag_o = dcqmem_tag_i;
//QMEM与DCache之间的信号
assign dcqmem_adr_o = qmemdmmu_adr_i;
assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
assign dcqmem_ci_o = qmemdmmu_ci_i;
assign dcqmem_we_o = qmemdcpu_we_i;
assign dcqmem_sel_o = qmemdcpu_sel_i;
assign dcqmem_tag_o = qmemdcpu_tag_i;
assign dcqmem_dat_o = qmemdcpu_dat_i;

or1200_qmem_top.v
or1200_spram_2048x32 or1200_qmem_ram(
      .clk(clk),   .rst(rst),
`ifdef OR1200_BIST
      .mbist_si_i(mbist_si_i), .mbist_so_o(mbist_so_o),.mbist_ctrl_i(mbist_ctrl_i),
`endif
`ifdef OR1200_QMEM_BSEL
.sel(qmem_sel),
`endif
`ifdef OR1200_QMEM_ACK
  .ack(qmem_ack),              //实际的RAM代码中并没有ack信号，所以这里是不需要的
`endif
.addr(qmem_addr[12:2]), .ce(qmem_en), .we(qmem_we),.oe(1'b1),
.di(qmem_di),.doq(qmem_do)
);

or1200_spram_2048x32.v
parameter aw = 11;                //地址线的宽度为11，数据线的宽度为32，所以共有8KB
parameter dw = 32;
reg [dw-1:0]mem [(1<<aw)-1:0];    //使用数组定义RAM，在综合的时候会将其综合为RAM单元
reg [aw-1:0]    addr_reg;
//使用mem.data初始化RAM，也就是初始化QMEM
initial $readmemh ( "mem.data", mem );
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};        //doq是读出的数据
always @(posedge clk or `OR1200_RST_EVENT rst)
    if (rst == `OR1200_RST_VALUE)
        addr_reg <=   {aw{1'b0}};                      //地址寄存
    else if (ce)
        addr_reg <=   addr;
always @(posedge clk)
    if (ce && we)
        mem[addr] <=  di;                              //写RAM

or1200_qmem_top.v
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit &
        qmemdmmu_cycstb_i;
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
assign qmem_di = qmemdcpu_dat_i;
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i :
        qmemimmu_adr_i;
`ifdef OR1200_QMEM_BSEL
    assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i :
qmemicpu_sel_i;
`endif

or1200_genpc.v
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we &
      (icpu_rty_i| genpc_refetch) ? icpu_adr_i :
      {pc[31:2], 1'b0, ex_branch_taken| spr_pc_we};
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));

or1200_ctrl.v
assign  no_more_dslot  =  (|ex_branch_op  &  !id_void  &  ex_branch_taken)  |
(ex_branch_op == `OR1200_BRANCHOP_RFE);
always @(posedge clk or `OR1200_RST_EVENT rst)
      if (rst == `OR1200_RST_VALUE)
        ex_branch_op <=  `OR1200_BRANCHOP_NOP;//or1200_defines.v中定义
                                                  //OR1200_BRANCHOP_NOP为0
        ……

or1200_wb_biu.v
  assign biu_ack_o= (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o &
          (wb_ack_cnt ~^ biu_ack_cnt);
  assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o &
          (wb_err_cnt ~^ biu_err_cnt)
  always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
    if (wb_rst_i == `OR1200_RST_VALUE)
            wb_fsm_state_cur <=  wb_fsm_idle;
                        //复位的时候wb_fsm_state_cur为wb_fsm_idle，所以上面的
                        //biu_ack_o、biu_err_o都为0
    else
        wb_fsm_state_cur <=  wb_fsm_state_nxt;
  end

or1200_genpc.v
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we &
      (icpu_rty_i | genpc_refetch) ?       //这里icpu_rty_i为1
      icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};

or1200_immu_top.v
wire[31:0]  icpu_adr_boot = boot_adr;
            // parameter boot_adr = `OR1200_ BOOT_ADR，即0x100
always @(`OR1200_RST_EVENT rst or posedge clk)
      if (rst == `OR1200_RST_VALUE) begin
      pcreg_default <=  `OR1200_BOOT_PCREG_DEFAULT;
                             //复位的时候pcreg_default为0x39
      pcreg_select <=  1'b1;
    end
    else if (icpu_adr_select) begin
        icpu_adr_default <=  icpu_adr_boot;
        icpu_adr_select  <=  1'b0;
    end
    else begin
        icpu_adr_default <=  icpu_adr_i;
    end
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
    if (icpu_adr_select)
        icpu_adr_o = icpu_adr_boot ;     //icpu_adr_select在复位的时候为1，所
                                         //以icpu_adr_o在复位的时候
                                         //值为OR1200_BOOT_ADR，即0x100
    else
        icpu_adr_o = icpu_adr_default ;

or1200_genpc.v
always @(posedge clk or `OR1200_RST_EVENT rst)
    if (rst == `OR1200_RST_VALUE) begin
      pcreg_default <= `OR1200_BOOT_PCREG_DEFAULT; //复位的时候pcreg_default为0x39
      pcreg_select <=  1'b1;// select async. value due to reset state
    end
else if (pcreg_select) begin
        pcreg_default <=  pcreg_boot[31:2];
        pcreg_select <=  1'b0;                       // select FF value
    end
    else if (spr_pc_we) begin
        pcreg_default <=  spr_dat_i[31:2];
    end
    else  if  (no_more_dslot  |  except_start  |  !genpc_freeze  &  !icpu_rty_i
& !genpc_refetch) begin
        pcreg_default <=  pc[31:2];
    end
assign  pcreg_boot = `OR1200_BOOT_ADR;          //就是0x100
always @(pcreg_boot or pcreg_default or pcreg_select)
    if (pcreg_select)                           //复位的时候pcreg_select为
                                                     //1，所以pcreg为pcreg_boot
                                                     //[31:2]，也就是0x40
        pcreg = pcreg_boot[31:2];
    else
        pcreg = pcreg_default ;
always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
        or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
        except_prefix)
    begin
    casez ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
    {2'b00, `OR1200_BRANCHOP_NOP}: begin
        pc = {pcreg + 30'd1, 2'b0};             //复位的时候pc为{0x40+1,00}，
                                                     //也就是0x104
        ex_branch_taken = 1'b0;
    end
  ……

or1200_if.v
assign  if_insn  =  no_more_dslot  |  rfe  |  if_bypass  ?  {`OR1200_OR32_NOP,
                    26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i :
                    {`OR1200_OR32_NOP, 26'h061_0000};

or1200_qmem_top.v
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit &
        qmemdmmu_cycstb_i;
                              //在最小系统中iaddr_qmem_hit始终为1，同时从上面的
                              //分析可知qmemimmu_cycstb_i为1，所以qmem_en为1
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
assign qmem_addr=(qmemdmmu_cycstb_i&daddr_qmem_hit)?qmemdmmu_adr_i:qmemimmu_adr_i;

or1200_lsu.v
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |ex_lsu_op;
          //这里du_stall是与Debug有关的信号，一般情况下为0，lsu_unstall与
          //except_align在复位的时候都为0，ex_lsu_op也为0，所以dcpu_cycstb_o为0
always @(posedge clk or `OR1200_RST_EVENT rst) begin
    if (rst == `OR1200_RST_VALUE)
        ex_lsu_op <=  `OR1200_LSUOP_NOP;     //复位的时候ex_lsu_op为0
……

or1200_qmem_top.v
always @(`OR1200_RST_EVENT rst or posedge clk)
    if (rst == `OR1200_RST_VALUE) begin
        state <=  `OR1200_QMEMFSM_IDLE;
        qmem_dack <=  1'b0;
        qmem_iack <=  1'b0;
    end
    else case (state)    // synopsys parallel_case
        `OR1200_QMEMFSM_IDLE: begin
            ……
            else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                        //qmem_ack始终为1
                state <= `OR1200_QMEMFSM_FETCH;
                qmem_iack <= 1'b1;
                qmem_dack <=  1'b0;
            end
        end
      ……

or1200_spram_2048x32.v
always @(posedge clk or `OR1200_RST_EVENT rst)
    if (rst == `OR1200_RST_VALUE)
        addr_reg <=  {aw{1'b0}};
    else if (ce)
        addr_reg <=  addr;           //addr_reg寄存地址信号，变为0x40

or1200_spram_2048x32.v
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};       //此时的addr_reg为0x40

or1200_qmem_top.v
assign qmemicpu_dat_o = qmem_iack? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;

or1200_if.v
assign  if_insn  =  no_more_dslot  |  rfe  |  if_bypass  ?  {`OR1200_OR32_NOP,
                    26'h041_0000}:saved?insn_saved:icpu_ack_i?icpu_dat_i:
                    {`OR1200_OR32_NOP, 26'h061_0000};
                              //此时icpu_ack_i为1，icpu_dat_i就是QMEM的输出

or1200_genpc.v
  assign  icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we &
          (icpu_rty_i genpc_refetch) ?
            icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};

or1200_qmem_top.v
always @(`OR1200_RST_EVENT rst or posedge clk)
    if (rst == `OR1200_RST_VALUE) begin
        state <=  `OR1200_QMEMFSM_IDLE;
        qmem_dack <=  1'b0;
        qmem_iack <=  1'b0;
    end
    else case (state)    // synopsys parallel_case
        `OR1200_QMEMFSM_FETCH: begin
            ……
            else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                              //qmem_ack始终为1
            state <= `OR1200_QMEMFSM_FETCH;
            qmem_iack <= 1'b1;
                qmem_dack <=  1'b0;
            end
        end
    ……

or1200_spram_2048x32.v
always @(posedge clk or `OR1200_RST_EVENT rst)
    if (rst == `OR1200_RST_VALUE)
        addr_reg <=  {aw{1'b0}};
    else if (ce)
        addr_reg <= addr//此时addr_reg为0x104

or1200_genpc.v
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));

or1200_genpc.v
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we &
      (icpu_rty_i | genpc_refetch) ?
        icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};